1. Field of the Invention
The present invention relates to an automatic wiring method and apparatus for a semiconductor package having a multi-tier bonding pad structure, in which the pads to be connected to a semiconductor chip are arranged in multiple rows, and also relates to an automatic identifying method and apparatus for a semiconductor package for identifying each pad, as to the row to which the pad belongs, in a multi-tier bonding pad arrangement in which the pads to be connected to a semiconductor chip are arranged in multiple rows.
2. Description of the Related Art
In a semiconductor package such as a PBGA or EBGA package, a wiring pattern is designed so as to connect the pads (for example, bonding pads or flip chip pads), to be electrically connected to electrode terminals on a semiconductor chip, to the vias (land portions) provided along the periphery thereof, or to connect between the vias. The designer, using a CAD system, designs wiring routes for a semiconductor package on a virtual plane through trial and error, but the problem is that this design procedure is extremely time and labor consuming.
Several methods have been proposed to solve this problem. For example, Japanese Unexamined Patent Publication No. 2002-083006 discloses a method in which only wiring routes are defined in advance in a rough wiring step, and then, in a wiring forming step, the wiring lines are laid automatically and uniformly by considering lines and spaces while checking them against the actual design rules. Further, Japanese Unexamined Patent Publication No. 2001-15637, for example, discloses a method in which combinations for interconnecting between a plurality of solder ball connection pads and a plurality of wire bond pads are automatically selected in order to generate optimum candidates for interconnecting them. On the other hand, Japanese Unexamined Patent Publication No. 2000-35986, for example, discloses a method for making interconnections, efficiently and in a short period of time, between an array of inner leads and any array of lands arranged in a matrix form around the periphery thereof.
The above prior art methods are intended for application to the so-called “single-tier bonding pad structure” in which the pads to be connected to a semiconductor chip are arranged in a single row.
On the other hand, the “multi-tier bonding pad structure” in which the pads are arranged in multiple rows has come into widespread use in recent years.
FIG. 34 is a diagram showing by way of example the nets to be routed on a semiconductor package having a multi-tier bonding pad structure. On the semiconductor package, wiring lines are routed in such a manner as to extend substantially radially from the pads, to be connected to a semiconductor chip C placed in the center of a substrate, toward the vias provided on the periphery thereof. In this figure, the nets to be connected to the vias from the pads (bonding pads) arranged in two rows for one of the four sides of the semiconductor chip C are shown by straight lines (i.e., rats).
FIG. 35 is a diagram showing an example of actual wiring on the semiconductor package having the multi-tier bonding pads shown in FIG. 34. In accordance with the nets to be connected, as shown by the rats in FIG. 34, the wiring pattern is designed so that the wiring lines between the pads and the vias or between the vias will not cross each other, as shown in FIG. 35. At the same time, the wiring lines must be routed so as to satisfy the design rules by considering the lines and spaces between the pads and the vias or between the vias.
FIGS. 36a to 36d are diagrams (part 1) for explaining a variation of the wiring routing in the multi-tier bonding pad structure. In the figures, reference characters B1 to B3 are identification numbers assigned to the pads, for convenience, and reference characters V1 to V3 are identification numbers assigned to the vias, for convenience.
As shown, in the three-tier bonding pad structure in which the pads B1 to B3 belong to different rows (tiers), when connecting the pad B1 to the via V1, the pad B2 to the via V2, and the pad B3 to the via V3, respectively, there are four possible wiring route patterns as shown in FIGS. 36a to 36d. 
FIGS. 37a to 37e are diagrams (part 2) for explaining a variation of the wiring routing in the multi-tier bonding pad structure. In the figures, reference characters B1 to B3 are identification numbers assigned to the pads for convenience, and reference characters V1 to V3 are identification numbers assigned to the vias for convenience.
As shown, in the three-tier bonding pad structure in which the pads B1 to B3 belong to different rows, when connecting between the pads B1 to B3 and the vias V1 to V3 in different combinations, there are five possible wiring route patterns as shown in FIGS. 37a to 37e. 
In this way, in the case of multi-tier bonding pads, the design becomes further complex because, compared with single-tier bonding pads, there are many possible variations for the wiring routes connecting between the pads and the vias.
Furthermore, with recent improvements in semiconductor package and printed wiring board technologies, coupled with increasing variety and complexity of their applications, the kinds of arrangements, for the pads to be connected to semiconductor chips, have been increasing in variety and number.
FIGS. 38 and 39 are diagrams showing examples of the single-tier bonding pad arrangement, and FIGS. 40 to 43 are diagrams each showing the bonding pads arranged in two rows as an example of the multi-tier bonding pad arrangement. FIG. 44 is a diagram showing the bonding pads arranged in three rows as an example of the multi-tier bonding pad arrangement. Generally, semiconductor chips are rectangular in shape, and FIGS. 38 to 44 each show the pads (bonding pads) to be connected to chip pads on one of the four sides of the semiconductor chip. In FIG. 44, reference characters B11 to B17, B21 to B23, and B31 are identification numbers assigned to the pads for convenience.
Generally, in the single-tier bonding pad arrangement, the pads B are arranged in a straight line as shown in FIG. 38 or in an arc as shown in FIG. 39. In some designs, the pads may be arranged in other ways, for example, in a shape combining a straight line and an arc, though this is not shown here.
On the other hand, in the multi-tier bonding pad arrangement, the pads B are arranged in multiple rows in straight lines as shown in FIG. 40, or in arcs as shown in FIGS. 41 and 44, or in a shape combining a straight line and an arc as shown in FIGS. 42 and 43.
As described above, in the case of the multi-tier bonding pad arrangement, the number of wire routing variations that can be designed is much larger than in the case of the single-tier bonding pad arrangement, and the reality is that, because of its complexity, the designer manually performs the design work by relying on his experience and on intuition. As the designer has to manually design the optimum routing free from crossings of wiring lines, while satisfying the design rules, by trial and error or by actually making wire connections and making necessary corrections, the design quality and the time required to complete the design greatly depend on the designer's skill, experience, and intuition.
To alleviate the burden on the designer and to achieve a wiring design of stable quality, several automatic wiring methods including those described above have been proposed for single-tier bonding pads, but in the case of multi-tier bonding pads, it is difficult to automate the wiring design work because of its complexity as well as the large variety of possible wiring routes.
Here, the CAD system used for wiring design can grasp information about the XY coordinates of each pad on a virtual plane as well as information about the width of each pad, but cannot grasp information about the way the pads are arranged. On the designer side, the row to which each pad belongs can be easily identified by visual inspection, but on the CAD system side, given only the information about the width of the pad and about its XY coordinates on the virtual plane, it is difficult to identify, for each pad, the row to which it belongs. For example, in FIG. 44, the pad B11 and the pad B22 have approximately the same Y-coordinate value on the virtual plane, but actually, they belong to different rows. In this way, it can be said that, while grasping the information about the width of each pad and about its XY coordinates on the virtual plane, how the pads having a variety of shapes and orientations are to be identified using a processing unit is also an issue of great importance.
In view of the above problem, it is an object of the present invention to provide an automatic wiring method and apparatus for automating wiring design work for a semiconductor package having a multi-tier bonding pad structure in which the pads to be connected to a semiconductor chip are arranged in multiple rows, and also provide an automatic identifying method and apparatus for a semiconductor package for accurately identifying each pad as to the row to which the pad belongs, in a multi-tier bonding pad arrangement in which the pads to be connected to a semiconductor chip are arranged in multiple rows.